Harmonic impedance scanning is an important means of harmonic resonance analysis and AC or DC filter design in HVDC. In this paper, the circuit superposition theorem is used to explain the test signal method which is suitable for HVDC harmonic impedance scanning. Based on the basic principle of the test signal method and how it has progressed in HVDC application research, a method of selecting harmonic source amplitude and an improved scanning method for reducing the influence of the initial phase of the harmonic source are proposed. Finally, taking the CIGRE first benchmark model as an example, the influence of harmonic source amplitude and initial phase on harmonic impedance scanning is quantitatively and qualitatively analyzed on a PSCAD/EMTDC simulation platform to verify that the proposed method can be used to further improve the reliability of harmonic impedance scanning results of HVDC, and provide a reference for actual HVDC project design. This work is supported by the Science and Technology Project of China Southern Power Grid (No. CGYKJXM20180485) and Sichuan Science and Technology Plan (No. 2019YJ0631).