| 引用本文: | 吴志勇,王晞阳,陈继林.一种基于FPGA并行加速的稀疏矩阵求解方法[J].电力系统保护与控制,2021,49(11):155-162. |
| WU Zhiyong,WANG Xiyang,CHEN Jilin.A method for solving a sparse matrix based on FPGA parallel acceleration[J].Power System Protection and Control,2021,49(11):155-162 |
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| 摘要: |
| 研究了电力系统电磁暂态仿真中最耗时的稀疏矩阵快速求解问题。采用了算法定义架构的设计思想，提出了一种DAG静态并行调度算法，并设计了与之相适配的硬件并行加速阵列架构。在设计实现中，针对电磁暂态仿真运算中稀疏矩阵求解的特性，采用了精确的节拍级硬件资源调度，实现了高度融合的软硬件协同加速。在此基础上，进行了该设计的测试及性能分析。实验结果表明，该结构和方法在电力系统稀疏矩阵运算中的性能优于通用CPU和GPU。 |
| 关键词: 稀疏矩阵 DAG 数据流机 静态调度 并行算法 现场可编程门阵列(FPGA) |
| DOI：DOI: 10.19783/j.cnki.pspc.200948 |
| 分类号: |
| 基金项目:国家电网有限公司总部科技项目“适应于电力系统应用的高性能计算技术研究与开发”(XTB17201900305) |
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| A method for solving a sparse matrix based on FPGA parallel acceleration |
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WU Zhiyong, WANG Xiyang, CHEN Jilin
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(1. National Supercomputing Center in Wuxi, Wuxi 214072, China;
2. China Electric Power Research Institute Co., Ltd., Beijing 100085, China)
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| Abstract: |
| This paper studies the most time-consuming sparse matrix fast solving problem in the electromagnetic transient simulation of a power system. It adopts the design idea of algorithm definition architecture, proposes a DAG static parallel scheduling algorithm, and designs a suitable hardware parallel to accelerate the array architecture. In the design and implementation, in order to solve the sparse matrix in the electromagnetic transient simulation operation, the precise beat-level hardware resource scheduling is adopted to realize the highly integrated software and hardware coordination acceleration. A design test and performance analysis is carried out. The results show that the structure and method performance is better than general-purpose CPU and GPU in the sparse matrix operation of a power system.
This work is supported by the Science and Technology Project of State Grid Corporation of China “Research and Development of High-performance Computing Technology Suitable for Power System Applications” (No. XTB17201900305). |
| Key words: sparse matrix DAG data-flow computer static scheduling parallel algorithm field programmable gate array (FPGA) |
